Using Vlsi to Reduce Serialization And Memory Traffic in Shared Memory Parallel
Using Vlsi to Reduce Serialization And Memory Traffic in Shared Memory Parallel
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Further details on the design of combining queues can, be found in [20]. The design of the RPC will be presented later in this section. For a detailed description of the implementation of a network for a planned 32-PE prototype, see [3].
4. 2. Flow Control The construction of the queues requires that there be an even number of packets per message and that switches distinguish even and odd cycles. At initialization, the parity of the cycle is the same as the parity of the stage to which the swit...ch belongs, so that cycles that are even for a switch are odd for its predecessors and successors while the cycle parity of the FPC and RPC in the same switch are identical. Reception of messages starts only at even cycles while transmission of messages starts only at odd cycles.
Each port consists of data bits and two protocol bits: a data valid bit (DV) traveling in the same direction as the data and a data accept bit (DA) traveling in the reverse direction. In addition, input ports receive a routing (RO) bit whose value at the first cycle of a message transmission indicates to which output port the message is destined.
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To quickly assess the difficulty of the text, read a short excerpt:
Further details on the design of combining queues can, be found in [20]. The design of the RPC will be presented later in this section. For a detailed description of the implementation of a network for a planned 32-PE prototype, see [3].
4. 2. Flow Control The construction of the queues requires that there be an even number of packets per message and that switches distinguish even and odd cycles. At initialization, the parity of the cycle is the same as the parity of the stage to which the swit...ch belongs, so that cycles that are even for a switch are odd for its predecessors and successors while the cycle parity of the FPC and RPC in the same switch are identical. Reception of messages starts only at even cycles while transmission of messages starts only at odd cycles.
Each port consists of data bits and two protocol bits: a data valid bit (DV) traveling in the same direction as the data and a data accept bit (DA) traveling in the reverse direction. In addition, input ports receive a routing (RO) bit whose value at the first cycle of a message transmission indicates to which output port the message is destined.
What to read after Using Vlsi to Reduce Serialization And Memory Traffic in Shared Memory Parallel?
You can find similar books in the "Read Also" column, or choose other free books by Susan Dickey to read onlineMoreLess
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